Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

paddsubs.uh Rd, Rx:<part>, Ry:<part> 

If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0];
If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0];
Rd[31:16] = SATU(ZE(operand1, 17) + ZE(operand2, 17), 16);
Rd[15:0] = SATSU(ZE(operand1, 17) - ZE(operand2, 17), 16);
 
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}

Rev1+

111

Rx

00000

Ry

0010001000

X

Y

Rd

3

4

5

4

10

1

1

4

2

paddsubs.sh Rd, Rx:<part>, Ry:<part> 

If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0];
If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0];
Rd[31:16] = SATS(SE(operand1, 17) + SE(operand2, 17), 16);
Rd[15:0] = SATS(SE(operand1, 17) - SE(operand2, 17), 16);
 
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}

Rev1+

111

Rx

00000

Ry

0010000110

X

Y

Rd

3

4

5

4

10

1

1

4

Description

Perform an addition and subtraction on the same halfword operands which are selected from the source registers. The resulting halfwords are saturated to unsigned halfwords (paddsubs.uh) or signed halfwords (paddsubs.sh) and then packed together in the destination register.

Status Flags:

Q:

Flag set if saturation occured in one or more of the partial operations.

V:

Not affected.

N:

Not affected.

Z:

Not affected.

C:

Not affected.